FIG. 1 is a schematic diagram illustrating a structure of a conventional buffer management system. As shown in FIG. 1, the buffer management system includes a buffer, an input module, an output module and a buffer manager.
The buffer is divided into multiple buffer blocks.
The input module requests the buffer manager for address pointers of idle buffer blocks for each input data packet, and after successfully parsing the input data packet, saves the input data packet respectively into the buffer blocks corresponding to the input data packet according to the requested address pointers and using a block as a unit.
The output module requests to look up the buffer manager for address pointers of buffer blocks corresponding to a data packet to be transmitted, reads the complete data packet from the buffer blocks in turn according to the found address pointers, and transmits the complete data packet.
Because the buffer blocks respectively storing continuous data of one data packet are not continuous, the buffer manager needs to maintain an address pointer linked list adapted to record a next address pointer of each requested address pointer. The buffer manager can thus continuously find the continuous data of one data packet and enable the output module to read and transmit the data packet.
In addition, the buffer manager is not only adapted to request for the address pointers and look up for the address pointers, but also to release the address pointers of the buffer blocks corresponding to the data packet after the output module transmits the complete data packet and the input module learns that the data packet is incorrectly-parsed.
FIG. 2 is a schematic diagram illustrating an internal logic structure of a conventional buffer manager. As shown in FIG. 2, the buffer manager includes the following.
An idle pointer unit, shown as a POINTER QUEUE (PTRQ), is a First In First Out memory (FIFO) with a width equal to the depth of an address pointer and with a depth equal to the total number of buffer blocks in the buffer. Idle address pointers of idle buffer blocks in the buffer are recorded in the PTRQ. FIG. 3 is a schematic diagram illustrating an example of an idle address pointer queue recorded in the PTRQ. During initialization, all the buffer blocks in the buffer are idle, and correspondingly, all the address pointers are recorded in the PTRQ as the idle address pointers.
An address request unit, when the input module starts to parse the input data packet, is adapted to request, from the idle address pointers recorded in the PTRQ, for the address pointers of the buffer blocks corresponding to each continuous block of data in the input data packet in turn, so that the input module can save a correctly-parsed data packet into the buffer blocks in the buffer.
A first address release information storing unit, shown as a RELAESE QUEUE 1 (RLSQ1) of the input module in FIG. 2, is a FIFO with a width equal to the depth of the address pointer. When parsing the input data packet, the input module can not learn whether the input data packet is incorrect until the end of the input data packet is parsed;
because the address pointers of the buffer blocks are requested corresponding to all the continuous blocks of data in the input data packet, if the input data packet is incorrect, the input module records requested address information of the incorrectly-parsed input data packet into the RLSQ1. The requested address information contains the address pointer of the header of the incorrectly-parsed input data packet, and the number of the buffer blocks occupied by the input data packet.
A linked list information unit is a Random Access Memory (RAM) with a width equal to the depth of the address pointer and with a depth equal to the total number of the buffer blocks in the buffer. In FIG. 2, the RAM is shown as an ADDR_LINK_RAM and is adapted to record the next address pointers inters of requested address pointers. Based on an arrangement sequence of the address pointers shown in FIG. 3, FIG. 4 illustrates an example of the next address pointers of the requested address pointers respectively recorded in the ADDR_LINK_RAM.
A linked list UpBuild unit writes a currently-requested address pointer into a position corresponding to a previously-requested address pointer in the ADDR_LINK_RAM so as to indicate that the currently-requested address pointer is the next address pointer pointed by the previously-requested address pointer.
A linked list Lookup unit, before the output module reads continuous blocks of data of one data packet from the buffer, looks up the next address pointers corresponding to the requested address points in the ADDR_LINK_RAM in turn so as to make the output module read the data packet from buffer blocks in the buffer.
A second address release information storing unit, shown as a RELAESE QUEUE 2 (RLSQ0) of the output module, is a FIFO with a width equal to the depth of the address pointer. After reading and outputting the complete data packet, the output module records address information of the output data packet into the RLSQ0. The address information contains the address pointer of the header of the output data packet and the number of the buffer blocks occupied by the output data packet.
An address release unit is adapted to release address pointers indicated by the address information recorded in the RLSQ1 and the RLSQ00 into the PTRQ. However, because the address information recorded in the RLSQ1 and the RLSQ0 only records the address pointers of headers and the number of the buffer blocks occupied by the data packets, only the address pointers of the headers of the data packets can be directly released while the address pointers of the buffer blocks corresponding to the other data blocks need be looked up in turn in the ADDR_LINK_RAM by the linked list Lookup unit.
As can be seen, in the buffer manager shown in FIG. 2, the PTRQ is the FIFO with the width equal to the depth of the address pointer and with the depth equal to the total number of the buffer blocks in the BUFFER. The FIFO occupies a huge number of hardware resources. Suppose that the width is 20 bits and the depth is 220, 20M bits of storage resources are required in order to implement the FIFO. However, the buffer manager is generally implemented by a Field Programmable Gate Array (FPGA) while it is difficult for the FPGA to provide such a huge number of resources. Similar to the PTRQ, the ADDR_LINK_RAM also requires a huge number of storage resources and thus can not be implemented by the FPGA either.
In addition, the conventional buffer manager shown in FIG. 2 needs to look up in the ADDR_LINK_RAM when the output module reads the data packet. Further more, because the address information which needs to be released and is provided by the input module and the output module only records the address pointers of the headers and the number of the buffer blocks occupied by the data packets, the conventional buffer manager also needs to look up in the ADDR_LINK_RAM once again when the address pointers are released. As a result, efficiency for releasing the address pointers is low, and in addition, abnormal packet loss may occur.